Summary of Research
This is a summary of the research performed by Algirdas A. Avižienis individually and in collaboration with his colleagues and graduate students in the time period 1955-2010. A.A. Avižienis is referred to as AA in the following text.
1. Signed-Digit Arithmetic with a Totally-Parallel Addition and Subtraction Algorithm
AA has invented the totally-parallel addition and subtraction algorithm that reduces the time of addition or subtraction of two operands with any number of digits to the time needed to add two digits [Aviz61]. The cost of the algorithm is the introduction of at least two redundant digit values in the symmetric signed-digit (s-d) representation, for example adding the values +6 and -6 to the decimal s-d representation with digit values +5 to -5.
The totally-parallel add/subtract algorithm was part of AA’s Ph.D. dissertation [Aviz60] at the Digital Computer Laboratory of the University of Illinois (UI DCL), completed in May 1960 and directed by James E. Robertson, who declined to be co-author of [Aviz61] because AA had invented the algorithm while on a year’s leave of absence from the UI DCL in 1958-59. AA also developed a multiplication algorithm and adapted Robertson’s division algorithm [Robe58] for signed-digit operands in the dissertation. AA was associated with the UI DCL as a Fellow in 1956-58, and as a Research Assistant, participating in the design of the ILLIAC II computer, in 1959-60.
The totally-parallel add/subtract algorithms are used for fast digital arithmetic because of the speed and modular structure of adder circuitry. The French science journal La Recherche in its special issue on „Numbers“ (July/August 1995) has highlighted this „Avižienis‘ algorithm“ as one of the most significant developments in computer arithmetic of the 20th century.
The 1961 paper “Signed-Digit Number Representations for Fast Parallel Arithmetic” [Aviz61] that presented the results of the dissertation has received 914 citations (as of May 15, 2010) according to the Google Scholar database. The recent increase of interest in Avizienis‘ s-d arithmetic is shown by the fact that 311 (34%) of the 914 citations have been added since January 1, 2008.
It is interesting to note that the decimal symmetric signed-digit representation with digit values +5 to -5 was first proposed by the French mathematician Augustin-Louis Cauchy in 1840 in the paper “Sur les moyens d’aviter les erreurs dans les calculs numeriques”, published in”Comptes rendus de l’ Academie des Sciences 11 (Paris 1840)” . However, Cauchy’s addition had carry and borrow propagation, similar to carry propagation in ordinary addition, and therefore was not faster. Cauchy’s motivation was to simplify addition, subtraction, and multiplication by eliminating the digit values 6,7,8,9 from those operations and therefore to reduce human errors in numerical computations. AA was not aware of Cauchy’s paper while writing his dissertation, and only learned about it during a visit to France in 2010. AA’s s-d representations differ from Cauchy’s by being redundant, that is, by using at least two more digit values than Cauchy.
In later research at the Jet Propulsion Laboratory of Caltech AA developed a multiple-precision addition and subtraction algorithm with the most significant digits (msd) being added first, and a multiplication algorithm in which the msd of the product is generated first [Aviz63]. These algorithms allowed the implementation of significant-digit arithmetic [Metr58] by means of a special “space-zero” digit [Aviz63]. AA also devised algorithms and building blocks for binary-compatible s-d arithmetic [Aviz64], [Aviz66] and a universal s-d Arithmetic Building Element that included multi-operand addition and array multiplication [Aviz70].
AA also investigated the theoretical aspects of redundancy in number representation systems [Aviz69], [Aviz75], and devised error detection algorithms for signed-digit arithmetic using low-cost arithmetic residue error detecting codes [Aviz81].
In more general arithmetic research AA devised a unified algorithmic specification of digital arithmetic based on Markov‘s theory of algorithms that used Iverson‘s APL notation [Aviz72]. He also supervised a dissertation exploring the bi-imaginary number system [Slek78].
2. Fault-Tolerant Computing at JPL
In September 1960 AA rejoined the Spacecraft Computers section of the NASA Jet Propulsion Laboratory (JPL) at the California Institute of Technology, Pasadena, California, where he had worked in 1955-56 after receiving the M.S.E.E. degree from the University of Illinois. At JPL he was asked to initiate research on building long-life computing systems for spacecraft intended to explore the planets of the solar system [Aviz87]. In the course of the research he originated the concepts of "fault tolerance“ and “fault-tolerant computing”, first described in the paper „Design of Fault-Tolerant Computers“ presented at the 1967 Fall Joint Computer Conference [Aviz67].
In that paper AA presents a classification of faults and errors, defines protective redundancy as the means to attain fault tolerance, and presents a taxonomy of its techniques. Protective redundancy is divided into two major categories: massive (or masking) and selective. Massive redundancy includes all masking methods described by Pierce as „failure tolerance“ [Pier65], while selective redundancy includes all methods of fault detection followed by a corrective action. Further AA cites examples of systems that could be called in part fault-tolerant and describes the design considerations and the organization of the fault-tolerant JPL-STAR (Self-Testing-And- Repairing) computer that was being built at that time. He presents criteria for the choice of redundancy techniques and illustrates them with the choices for JPL-STAR.
At JPL AA organized and directed the JPL-STAR research project from 1960 to 1972. This effort resulted in the construction, demonstration, and evaluation of the experimental STAR computer, for which he received U.S. Patent No. 3,517,171, "Self-Testing and Repairing Computer" granted on June 23, 1970 and assigned to NASA [Aviz70]. The 17-page patent, filed October 30, 1967, describes the JPL-STAR design in detail. The Test-And-Repair Processor TARP of STAR is probably the first instance of a complete “service processor” on record.
The paper [Aviz71] that described the JPL STAR computer received the Best Paper award of the IEEE Transactions on Computers in 1971. During the design effort AA did basic research on the application of arithmetic error detection codes that were used in the STAR computer [Aviz71a].
In 1969, JPL began designing the Thermoelectric Outer Planet Spacecraft (TOPS) intended for the 15-year „Grand Tour“ of four outer planets [A&A70], and STAR was to be the on-board computer. However, the war in Vietnam led to budget limitations for NASA and TOPS was cancelled in 1972. The Grand Tour TOPS spacecraft was replaced by the much simpler Voyager 1 and Voyager 2 spacecraft that were launched in 1977 and are still sending science data from outside of the solar system 33 years later. Some of the STAR fault tolerance techniques were adapted for the Voyager on-board computers.
AA continued to serve as a consulting Academic Member of Technical Staff at JPL until 1982, when he assumed the chairmanship of the UCLA Computer Science Department. A summary of research performed at JPL by AA and his colleagues is presented in [Aviz87].
In further efforts to advance the development of fault-tolerant computing, AA organized two successful professional groups. The IEEE CS Technical Committee on Fault-Tolerant Computing (FTC) was founded in 1969. AA served as the founding Chair and organized (as General Chair) the first International Symposium on FTC in Pasadena, CA, co-sponsored by JPL, in 1971. The 40th meeting of this series of conferences takes place in Chicago in 2010. AA also served as founding Chair of the IFIP Working Group 10.4 “Reliable Computing and Fault Tolerance” that was established in 1980 and is holding its 58th meeting in June 2010.
3. Low-Cost Arithmetic Error-Detecting and Error–Correcting Codes
The JPL-STAR (Self-Testing-And-Repairing) computer needed low-cost error detection since limited power resources did not allow complete replication of various subsystems, including the arithmetic unit. For this reason AA in 1963 [Aviz63a] started an investigation of the feasibility of using AN and residue arithmetic error codes that were only recently described in technical literature.
AA defined „low-cost“ arithmetic codes and investigated their effectiveness, then succesfully applied them in the STAR design [Aviz67a], [Aviz71a], including the algorithms for the design of an entire arithmetic unit for error-coded operands [Aviz73a]. As a by-product of this investigation AA also devised multi-residue codes [Aviz69a]. Later he devised and developed two-dimensional arithmetic codes [Aviz85a], [Aviz86] and error-detection codes for signed-digit operands [Aviz81].
4. Fault-Tolerant Computing at UCLA
Concurrently with the effort at JPL, AA had joined the faculty of the University of California, Los Angeles (UCLA) in 1962. He was promoted to full Professor in 1972, and to Faculty of Highest Distinction in 1986. He served as Chair of the Computer Science Department in 1982-85. Since 1994 he is Distinguished Professor Emeritus of the Computer Science Department.
Fault tolerance research at UCLA during the 1962-72 period was characterized by a very effective collaboration with the JPL-STAR project at JPL. The excellent laboratory facilities and expert technicians at JPL enabled the design, construction, and evaluation of the experimental STAR computer, while the academic environment at UCLA provided the opportunity to the researchers to present their results and insights through the rigorous form of Ph.D. dissertations. The STAR computer effort led to Ph.D. dissertations by F. P. Mathur, G. C. Gilley, D. A. Rennels and J.A. Rohr.
The severely limited research budget at JPL made it necessary to look for new sources of support. A major research effort began at UCLA in July of 1972, when AA received as Principal Investigator the five-year, $ 887,900 research grant "Fault-Tolerant Computing" from the U.S. National Science Foundation and established the UCLA Reliable Computing and Fault Tolerance research group that later evolved into the Dependable Computing and Fault-Tolerant Systems (DC & FTS) Laboratory. Further research grants and contracts from NSF, the Office of Naval Research, the Federal Aviation Administration, NASA, the State of California, and industry raised the total funding received by AA until 1990 to over $3 million as PI and another $4 million as a Co-PI.
During his tenure at UCLA AA supervised the completion of 29 Ph.D. dissertations and was the author or co-author of over 200 publications. Twelve UCLA faculty members have served as his Co-PIs, and over 50 graduate students and over 20 visiting researchers from Europe, Brasil, Japan, and China have taken part in research at the DC&FTS Laboratory. A broad range of research problems has been addressed, including fault-tolerant architectures for long-life computers, distributed systems, supercomputers, and real-time applications, modeling and evaluation of fault-tolerant systems, fault tolerance in associative processors and database machines, fault-tolerant VLSI design, arithmetic error detecting and correcting codes, design of self-checking PLA's, fault-tolerant computer communications, software fault tolerance, design diversity, correctness and usability of formal specifications, application of fault tolerance techniques in computer security [Jose88], taxonomies, and design methodologies for fault-tolerant systems.
An extensive summary and bibliography of the research results obtained at JPL and at UCLA until 1985 are presented in [Aviz87]. The following sections describe the areas of fault tolerance in which AA has contributed fundamental innovations while working at UCLA.
5. Tolerance of Design Faults by N-Version Programming and Design Diversity
In 1975 AA initiated research on the tolerance of design faults („bugs“) in computer software. His original approach was first called „redundant programming“ [Aviz75a] and then renamed „N-version programming“ (NVP) [Aviz77] that is the independent generation of two or more (N) programs for the same task. The programs are executed concurrently and their results are compared by a decision algorithm that chooses the most likely consensus result.
The research consisted of a series of experiments which provided insights to develop a methodology and to generalize the approach to the concept of „design diversity“ [Aviz82] that is applicable to design faults in hardware, man-machine interfaces and all other aspects of computing and communications [Aviz84].
It is important to note that from the beginning of the research the goal of NVP was to minimize the probability that residual software design faults would lead to an erroneous consensus decision by causing similar errors to occur in the majority of versions at a decision („cross-check“) point. The goal was to be attained by effective isolation and planned diversification of the N efforts. Diversity may be achieved along various dimensions, e.g., specification languages, specification writers, programming languages, programmers, algorithms, data structures, development environments, and testing methods. Some confusion has been caused by the erroneus claim in some publications that NVP naively assumed independence (i.e., dissimilarity) of the errors.
In the course of the experiments at UCLA it became evident that the general- purpose campus computing services were poorly suited to support the systematic execution, instrumentation, and observation of N-version fault-tolerant software. In order to provide a research facility for experimental investigations of design diversity as a means of achieving fault-tolerant systems, the UCLA Reliable Computing and Fault Tolerance research group designed and implemented the DEDIX (DEsign Diversity eXperiment) system, a distributed supervisor and testbed for multiple-version software, at the UCLA Center for Experimental Computer Science [Aviz85]. The purpose of DEDIX was to supervise and to observe the execution of N diverse versions of an application program functioning as as fault-tolerant N-version software unit. DEDIX also provided a transparent interface to the users, versions, and the input/output system, so that they need not be aware of the existence of multiple versions and recovery algorithms.
In 1987 the “Six Language” experiment was performed with support from Sperry Commercial Flight Systems, Phoenix AZ, in which six teams of two programmers each used six dif-ferent programming languages (Pascal, C, Modula-2, Ada, Lisp, and Prolog) to write a flight control program. The goal was to study the diversity that can be attained by the use of very different languages [Aviz88]. The results of this and preceding studies have been used in at least one critical application, which is the primary flight control computer system of the Boeing 777 airliner.
The results of the first ten years of NVP and design diversity research are presented in [Aviz85]. A full exposition of NVP methodology is presented in [Aviz95]. The recent impact of this research is seen in the number of citations as reported by Google Scholar on May 15, 2010. The number in parentheses shows the number of citations added after January 1, 2008. The citations are [Aviz85] : 641 (276=43%), [Chen78] : 329 (145=44%), [Aviz84] :306 (123=40%), [Aviz77]: 291 (112=38%).
6. Design Methodology Research and a Design Paradigm
The specification and design of the STAR computer at JPL involved much improvisation and experimentation with design alternatives. It became apparent that the lessons learned during this process could serve as the foundation for a more orderly approach that would utilize a set of guidelines for the choice of fault masking, error detection, diagnosis, and system recovery tech-niques.
The first effort to present such guidelines appeared in the 1967 Fall Joint Computer Conference paper "Design of Fault-Tolerant Computers" [Aviz67]. This paper introduced the concept of a "fault-tolerant system", presented a classification of faults and errors, and outlined the taxonomy of alternate forms of protective redundancy: masking, error detection, diagnosis, and recovery techniques. Three causes of faults: undetected design errors, random failures of components or connections, and externally induced malfunctions were identified.
Next the paper presented the criteria for choices between "massive" (i.e., masking) and "selective" application of protective redundancy. The design of the JPL STAR computer was used to illustrate the application of these criteria in choosing the fault tolerance techniques for a spacecraft computer that had long life and autonomy requirements with strict weight and power constraints. The 47 references covered the most relevant published work to mid-1967.
The earlier book "Failure-Tolerant Computer Design" by W. H. Pierce [Pier65] served as an important reference; however, it must be noted that Pierce's definition of "failure tolerance" corresponded exactly to fault masking in logic circuits, including voting, adaptive, and interwoven logic, redundant relay contact networks, and application of Hamming’s error correcting codes as a masking technique. It is a definitive work on masking forms of redundancy that were known at that time. However, neither error detection, nor fault diagnosis, nor recovery techniques were included as elements of Pierce's "failure-tolerant" computers.
The 1967 paper was the first of a sequence of publications that formulated an evolving view of fault-tolerant computing as the consequence of a judicious introduction of fault tolerance and fault avoidance during system design. Two fundamental classes of faults - those due to physical causes, and those due to human mistakes and oversights were considered. This evolving view was presented in a series of papers on the techniques, scope, and aims of fault tolerance. The key contributions to this series are: [Aviz 72a], [Aviz 75b], [Aviz 77a], [Aviz 78], [Aviz82], [Aviz84], [Aviz 86a], [Aviz87a], [Aviz89], [Aviz95], [Aviz97], [Aviz00], [Aviz01a], [Aviz04], [Aviz06].
The unifying theme of these papers has been the evolution of a design paradigm for fault-tolerant systems that guides the designer to consider fault tolerance as a fundamental issue throughout the design process. The series shows a progressive refinement of concepts and an expansion of the scope to include the tolerance of "human-made" design and interaction faults and of malicious faults due to human adversaries. Other later themes are the balancing of performance and fault tolerance objectives during system partitioning and the integration of subsystem recovery procedures into a multi-level recovery hierarchy [Aviz97]. Strong emphasis is also placed on the application of design diversity in all parts of a multichannel system in order to attain tolerance of design faults.
The concept and structure of a „fault tolerance infrastructure“ that is analogous to the human immune system has been introduced in [Aviz00a]. Design principles based on the analogy have been called an „immune system paradigm“ [Aviz00], [Aviz01a], [Aviz06].
A closely related effort was the development of a paradigm for the qualitative evaluation of the fault tolerance attributes of complex system designs. This "inverse" of the design paradigm was developed as part of the research related to the Advanced Automation System for air traffic control in the U. S. [Aviz 87b], [Aviz87c].
7. Taxonomy of Dependable and Secure Computing
In the seminal paper [Aviz67] AA introduced the original concept of fault tolerance, presented a classification of faults and errors, identified the causes of faults, defined protective redundancy as the means to attain fault tolerance, and presented a taxonomy of its techniques. He also presented criteria for choice of redundancy techniques and illustrated them with the choices for JPL-STAR.
The paper [Aviz67] initiated a life-long effort to create a methodology for the design of fault-tolerant computers (discussed in the preceding section) and to create a growing taxonomy of dependable computing. AA continued to introduce new concepts and describe their relationships with the concepts developed by other researchers in a series of papers that developed a taxonomy of dependable computing [Aviz75b], [Aviz78], [Aviz82], [Aviz82a], [Aviz83], [Aviz10] for which he also enlisted the cooperation of distinguished colleagues [Aviz84], [Aviz86a], [Aviz99], [Aviz01], [Aviz04].
The most recent taxonomy paper [Aviz04] published in 2004 was co-authored by J.-C. Laprie, B. Randell and C. Landwehr and by June 1, 2010 has already gathered 1219 citations as reported by Google Scholar, 841 (69%) of which were recorded after Jan. 1, 2008. This paper adds the taxonomy of secure computing to that of dependable computing. A preliminary version [Aviz01] of this paper was published as a technical report in 2001 and has accumulated 474 citations.
Very valuable support for the taxonomy research effort has come from AA‘s participation in the activities of IFIP Working Group 10.4 (Dependable Computing and Fault Tolerance) which he organized in 1980 and chaired until 1986, and quite especially from the discussions of fundamental concepts of fault tolerance that have been taking place since the very first meeting of the WG 10.4 in 1981. Most specifically, the work of Dr. Jean-Claude Laprie has been of great value, especially through collaboration during his stay as a Visiting Professor at UCLA in 1985 [Aviz 86a] and via a three-year NSF-CNRS International Cooperation grant later.
In 2006-2009 AA served as the Project Leader for Vytautas Magnus University and a member of the Executive Board of the EU Network of Excellence project ReSIST (Resilience for Survivability in IST) that included 18 partners from 8 EU countries and Switzerland. He also was Leader of the Special Interest Group on Resilience Ontology of the ReSIST NoE. Part of the results of the work by SIG ResOn is reported in [Aviz09]. The ontology is a generalized taxonomy that includes relationships other than inclusion, e.g., causation.
[Aviz60] Avizienis, A. "A Study of Redundant Number Representations for Parallel Digital Computers," Report No. 101, Digital Computer Laboratory, Univ. of Illinois, May 20, 1960.
[Aviz61] Avizienis, A. "Signed-Digit Number Representations for Fast Parallel Arithmetic”, IRE Trans. on Electronic Computers, EC-10:389-400, 1961.
[Aviz63] Avizienis, A. "On a Flexible Implementation of Digital Computer Arithmetic," Information Processing 1962, Popplewell, C.M., ed., North Holland Publishing Co., Amsterdam, 1963, p. 664-670.
[Aviz63a] Avizienis, A. "Coding of Information for a Guidance Computer with Active Redundancy," JPL Space Programs Summary, 37-22, IV:9-12, C.I.T., August 31, 1963.
[Aviz64] Avizienis, A. "Binary-Compatible Signed-Digit Arithmetic," AFIPS Conf. Proc., San Francisco, 1964, vol.26, pp. 663-672.
[Aviz66] Avizienis, A. "Arithmetic Microsystems for the Synthesis of Function Generators," Proc. of the IEEE, 54:1910-1919, December 1966.
[Aviz67] Avizienis, A. "Design of Fault-Tolerant Computers," AFIPS Conference Proceedings, Fall JCC 1967, vol. 31, pp:733-743, Anaheim, CA , October 1967.
[Aviz67a] Avizienis, A. "Concurrent Diagnosis of Arithmetic Processors," Digest of the 1st Annual IEEE Computer Conference, pp. 34-37, September 1967.
[Aviz69] Avizienis, A. "On the Problem of Computational Time and Complexity of Arithmetic Functions," Proc. of the ACM Symposium on the Theory of Computing, May 1969, Los Angeles, p. 255-258.
[Aviz69a] Avizienis, A. "Digital Fault Diagnosis by Low-Cost Arithmetical Coding Techniques," Proc. of the Purdue Univ. Centennial Year Symposium on Information Processing, April 1969, p. 81-92.
[Aviz70] Avizienis, A., Tung, C. "A Universal Arithmetic Building Element (ABE) and Design Methods for Arithmetic Processors," IEEE Trans. on Computers, C-19:733-745, August 1970.
[Aviz70] U.S. Patent No. 3,517,171, "Self-Testing and Repairing Computer" granted on June 23, 1970 to A.Avizienis and assigned to NASA.
[Aviz71] Avizienis, A., Gilley, G.C., Mathur, F.P., Rennels, D.A., Rohr, J.A., Rubin, D.K. "The STAR (Self-Testing-and-Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design," IEEE Trans. on Computers, C-20:1312-1321, November 1971
[Aviz71a] Avizienis, A. "Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design," IEEE Trans. on Computers, C-20:1322-1330, November 1971
[Aviz72] Avizienis, A. "Digital Computer Arithmetic: A Unified Algorithmic Specification," Proc. of the Symposium on Computers and Automata, Polytechnic Institute of Brooklyn, 1972, p. 509-572.
[Aviz72a] Avizienis, A. "The Methodology of Fault-Tolerant Computing," Proc. of the 1st USA-Japan Computer Conference, Tokyo, October 1972, p. 405-413.
[Aviz73a] Avizienis, A. "Arithmetic Algorithms for Error-Coded Operands," IEEE Trans. on Computers, C-22:567, 572, June 1973.
[Aviz75] Avizienis, A. "Redundancy in Number Representations as an Aspect of Computational Complexity of Arithmetic Functions," Proc. of the 3rd IEEE Symposium on Computer Arithmetic, Dallas, November 19-20, 1975, pp. 87-89.
[Aviz75a] Avizienis, A. "Fault-Tolerance and Fault-Intolerance: Complementary Approaches to Reliable Computing," Proc. of the 1975 Int. Conf. on Reliable Software, Los Angeles, April 1975, p. 458-464.
[Aviz75b] Avizienis, A. "Architecture of Fault-Tolerant Computing Systems," Proc. of 1975 Int. Symposium on Fault-Tolerant Computing, Paris, June 1975, p. 3-16.
[Aviz77a] Avizienis, A. "Fault-Tolerant Computing: Progress, Problems, and Prospects," Information Processing 77, Proc. of the IFIP Congress 1977, Toronto, August 8-12, 1977, pp. 405-420.
[Aviz77] Avizienis, A., Chen, L. "On the Implementation of N-Version Programming for Software Fault-Tolerance During Execution," Proc. of COMPSAC 77, (IEEE Computer Society's 1st Int. Computer Software & Applications Conf.), Chicago, November 8-11, 1977, p. 149-155.
[Aviz78] Avizienis, A. "Fault-Tolerance: The Survival Attribute of Digital Systems," Proc. of the IEEE, October 1978, 66-10:1109-1125.
[Aviz81] Avizienis, A. "Low Cost Residue and Inverse Residue Error-Detecting Codes for Signed-Digit Arithmetic," Proc. 5th IEEE Symposium on Computer Arithmetic, Ann Arbor, MI, May 18, 1981, pp. 165-168.
[Aviz82] Avizienis, A. "Design Diversity- the Challenge of the Eighties," Digest FTCS-12: 1982 Int. Symp. on Fault-Tolerant Computing, Santa Monica, CA, June 1982, 44-45.
[Aviz82a] Avizienis, A. "The Four-Universe Information System Model for the Study of Fault-Tolerance," Digest FTCS-12: the 1982 Int. Symposium on Fault-Tolerant Computing, Santa Monica, CA, June 1982, pp. 6-13.
[Aviz83] Avizienis, A. "Framework for a Taxonomy of Fault-Tolerance Attributes in Computer Systems," Proc., 10th Int'l Symposium on Computer Architecture, Stockholm, Sweden, June 1983, pp. 16-21.
[Aviz84] Avizienis, A., Kelly, J.P.J. "Fault Tolerance by Design Diversity: Concepts and Experiments," Computer, August 1984, 17-8:67-80.
[Aviz85] Avizienis, A. "The N-Version Approach to Fault-Tolerant Software," IEEE Transactions on Software Engineering, Vol. SE-11(12), pp. 1491-1501, December 1985.
[Aviz85a] Avizienis, A. "Arithmetic Algorithms for Operands Encoded in Two-Dimensional Low-Cost Arithmetic Error Codes," Proc. 7th IEEE Symp. on Computer Arithmetic, U. of Illinois, pp. 285-292, May 1985
[Aviz86] Avizienis, A. "Two-Dimensional Low-Cost Arithmetic Residue Codes: Effectiveness and Arithmetic Algorithms," Digest of Papers, 16th Int. Symp.on Fault-Tolerant Computing, Vienna, Austria, pp. 330-336, 1986
[Aviz86a] Avizienis, A., Laprie, J.C. "Dependable Computing: From Concepts to Design Diversity," Proceedings of the IEEE, Volume 74, Number 5, pp. 629-638, May 1986
[Aviz87a] Avizienis, A. "A Design Paradigm For Fault-Tolerant Systems," Proceedings of the AIAA Computers In Aerospace VI Conference, Wakefield, Massachusetts, pp. 52-57, October 7-9, 1987.
[Aviz87b] Avizienis, A., Ball, D.E. "On The Achievement Of A Highly Dependable And Fault-Tolerant Air Traffic Control System," Computer, Volume 20, Number 2, pp. 84-90, February 1987
[Aviz87c] Avizienis, A. "The Dependability Problem: Introduction and Verification of Fault Tolerance for a Very Complex System," Proceedings of the 1987 Fall Joint Computer Conference, Dallas, Texas, pp. 89-93, October 25-29, 1987.
[Aviz88] Avizienis, A., Lyu, M.R., Schutz, W. "In Search Of Effective Diversity: A Six-Language Study Of Fault-Tolerant Flight Control Software," Proceedings of the 18th International Symposium on Fault-Tolerant Computing (FTCS-18), Tokyo, Japan, pp. 15-22, June 27-30, 1988.
[Aviz89] Avizienis, A. "Software Fault-Tolerance," Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, G.X. Ritter (Ed.), Elsevier Science Publishers, B.V. North Holland, San Francisco, CA, pp. 491-498, 1989.
[Aviz95] Avizienis, A., “The methodology of N-version programming”, Ch. 2 in Software Fault Tolerance, M.R. Lyu, editor, John Wiley & Sons Ltd., 1995, pp. 23-46
[Aviz97] Avizienis, A. “Toward systematic design of fault-tolerant systems”, IEEE Computer, vol.30, no.4, April 1997, pp. 51-58.
[Aviz99] Avizienis, A., He, Y., “Microprocessor entomology: a taxonomy of design faults in COTS microprocessors”, Dependable Computing for Critical Applications 7, Springer-Verlag Wien New York, 1999, pp. 3-23.
[Aviz00] Avizienis, A., “Design diversity and the immune system paradigm: cornerstones for information system survivability”, Proc. 3rd Information Survivability Workshop ISW-2000, Boston, MA, October 2000.
[Aviz00a] Avizienis, A., “A fault tolerance infrastructure for dependable computing with high-performance COTS components”, Proc. DSN 2000, 30th IEEE/IFIP Int. Conference on Dependable Systems and Networks, New York, NY, June 2000, pp. 492-500
[Aviz01] Avizienis, A., Laprie, J.-C., Randell, B., Fundamental Concepts of Dependability, LAAS Report no. 01-145, Newcastle University Report no. CS-TR-739, UCLA Report no. 010028, 2001
[Aviz01a] Avizienis, A. Avizienis, R., “An immune system paradigm for the design of fault-tolerant systems”, Proc. Workshop 3: Evaluating and Architecting Systems for Dependability (EASY), at DSN 2001, Goteborg, Sweden, July 2001.
[Aviz04] Avizienis, A., Laprie, J.-C., Randell, B., Landwehr, C., “Basic concepts and taxonomy of dependable and secure computing“, IEEE Trans. On Dependable and Secure Computing, vol.1, no.1, 2004, pp. 11-33.
[Aviz04a] Avizienis, A., “Dependable systems of the future: what is still needed ?” in Building the Information Society, R. Jacquart, ed., Proc. IFIP 18th World Comp Congress, Toulouse, France, Springer, Aug.2004, pp. 79-90.
[Aviz06] Avizienis, A.,“An immune system paradigm for the assurance of dependability of collaborative self-organizing systems”, in Biologically-Inspired Cooperative Computing, Y. Pan, ed., Proc. IFIP 19th World Comp. Congress, Santiago, Chile, Springer Boston, Aug.2006, pp. 1-6.
[Aviz09] Avizienis, A., Grigonyte, G., Haller, J., von Henke, F., Liebig, T., Noppens, O., “Organizing knowledge as an ontology of the domain of resilient computing by means of natural language processing – an experience report”, Proc. of FLAIRS-22, 22nd International Florida Artificial Intelligence Research Society Conference, Sanibel Island, FL, May 2009
[Aviz10] Avizienis, A., “On the dependability of scientific and technical texts”, Proc. DSN 2010, 40th IEEE/IFIP Int. Conference on Dependable Systems and Networks, Supplemental volume, Chicago, IL, June 2010.
[A&A70] ‘TOPS Outer Planet Spacecraft”, special issue, Astronautics and Aeronautics, vol.8, September 1970.
[Jose88] Joseph, M.K., Avizienis, A. "A Fault Tolerance Approach To Computer Viruses," Proceedings of the 1988 IEEE Symposium On Security And Privacy, Oakland, California, pp. 52-58, April 18-21, 1988.
[Metr58] Metropolis, N., Ashenhurst, R.L., “Significant digit computer arithmetic”, IRE Trans. on Electronic Computers, vol. EC-7, (1958), pp.265-267.
[Pier65] Pierce, W.H., Failure-Tolerant Computer Design, Academic Press, New York and London, 1965.
[Robe58] Robertson, J.E., “A new class of digital division methods”, IRE Trans. on Electronic Computers, vol/. EC-7, (1958), pp. 218-222.
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Last updated 2010.06.08